The present invention relates to a start and stop control apparatus for a serial data transmission system.
A proper data transmission requires some data transmission controls. In the asynchronous data transmission system, information is transmitted in a series of pulses. It is necessary, therefore, to clarify the section of the pulses representing one unit of information, e.g. a character. This necessitates the synchronization between transmission and receiving sides. The start and stop control apparatus is a timing or control apparatus. In the start and stop control apparatus, an input data is of a serial data in which one bit pulse corresponds to, for example, 8 or 16 clock pulses. The data is provided at the beginning with a start bit pulse and at the end with a stop bit pulse. The synchronization is taken to the data in each data frame bounded by the start bit pulse and the stop bit pulse. In the conventional start and stop control apparatus, the start bit pulse is allotted by a pregiven number of pulses, for example, 16 clock pulses, and the 16th/2 pulse, i.e. the 8th pulse, is used for data sampling. However, in the prior art start and stop control apparatus the basic clock pulse for the data sampling is asynchronous with respect to the data to be transmitted and received, the start bit pulse is fixed with 16 clock pulses, and the 8th pulse of 16 clock pulses, is used as the sampling pulse for data sampling. Accordingly, where some reason causes the frequency of the clock pulses to change, the width of the start bit pulse is changed relative to the frequency of the clock pulse. As the result, when the respective pulses of the data are sampled by the sampling pulse corresponding to the center of the start bit pulse having the changed pulse width, the data sampling is shifted off from the center of the data bit pulse as the data sampling approaches the last data bit pulse in the data frame. Finally, the last data pulse is sampled in a state shifted off from the center of the pulse more than 8 clock pulses, as a result of accumulation of the successive shifting off. This causes a transmission error.
Let us consider now the case that the start and stop control apparatus is applied for the data transmission between a data processor and an input/output device (I/O device). In the case, the data transmission from the data processor needs individual clock pulse generators for the serial interface and the I/O device. The reason for this is that I/O devices have transmission rates peculiar to them, respectively, for example, 110 bit/sec for the teletype, 9600 bit/sec for the cathode ray tube display. It is desirable that the clock pulse from the clock pulse generator at the transmission side is made in synchronism with that of the clock pulse generator at the I/O device. In this case, in addition to the data bus, a control bus, for example, must be provided, with the result that, if the I/O device is located at a remote place, the start and stop control apparatus is disadvantageous from an economical standpoint, and it is impossible to correctly transmit high frequency pulses.